Case Study: Scaling Next-Gen AI Hardware (The 64k Neuromorphic Processor)
1. Executive Summary
Development and characterization of a 16-core, 64k-synapse memristive neuromorphic processor. My primary focus was architecting a scalable digital-to-analog interface and developing automated calibration algorithms to overcome severe analog hardware limitations, transforming a rigid lab prototype into a highly adaptable, tape-out-ready system.
2. The Challenge
Scaling analog neuromorphic chips exponentially increases hardware mismatching, which can render the spiking neural network unusable for real-world inference. Furthermore, the legacy testing infrastructure was highly inefficient: every new experiment required rewriting and recompiling VHDL/Verilog code for the FPGA. This created severe bottlenecks for R&D iteration, blocked scalability, and made the system impossible to use for software-focused researchers.
3. My Role & Execution
- Algorithmic Hardware Calibration: Engineered a mixed HW/SW automated calibration loop that iteratively tests neurons to find optimal thresholds. This intelligent software layer effectively masked the analog mismatching, standardizing neural behavior across the chip.
- Scalable Architecture Redesign: Completely overhauled the FPGA digital controller. Replaced a rigid, hardcoded setup with a unified, dynamic architecture based on AXI standards (easily adaptable to SPI, I2C, or PCIe).
- Productization & Future-Proofing: Designed the digital layer to be foundry-ready for future on-chip integration. Enabled dynamic configuration of cores, memristor management, and neuron control on the fly—without needing new bitstreams. Designed the system to easily support future software or hardware STDP (Spike-Timing-Dependent Plasticity) expansions.
4. The Impact & Deliverables
- Performance Leap: The automated calibration algorithms improved inference accuracy by over 70% in key tests, making the scaled-up hardware viable for complex tasks like N-MNIST classification.
- R&D Operational Efficiency: Eliminated the need for constant VHDL recompilation, drastically reducing experiment turnaround times from hours/days to minutes, accelerating the entire team’s workflow.
- System Flexibility: Delivered a robust, high-level user interface (Python-based) that allowed researchers to execute complex SNN configurations simply by interacting with a register bank, bridging the gap between deep hardware and high-level software.
Publications:
- A multi-core memristor chip for Stochastic Binary STDP
- New self-calibration algorithm for programmable multi-core memristor-CMOS chip for neuromorphic computing
5. More
About MemM-Scales project
Tech Stack
- Core: SNN, ST 130nm HCMOS9A, CEA-Leti MAD200 RRAM Memristors
- Control: SoC-FPGA, AMBA-AXI4, Python, Verilog
- Management: GitLab, Project Management methodologies